1. Field of the Invention
The present invention relates to a semiconductor memory device by which a multidirection data selection, especially a two or more direction data read and/or write in a logical bit map space, is enabled. More particularly, it relates to an improved semiconductor memory device having a chip which includes a multidirection data selection means and an address scramble means for converting an external address expressed in an easy usable form into an internal address to be used by the multidirection data selection means and a decoder connected to a memory cell array.
2. Description of the Related Art
In an image data processing system, for example, in a computer tomography (CT) scanning system, three dimensional bit map data are used and each data has a color and gradation indicating density. In the CT scanning system or the like, a high-speed reading of a plurality of data in a X-, Y- or plane-direction of a three dimension bit map space is required.
Conventional memory devices are essentially accessed in only one direction, for example, by a word line and bit lines. However, the conventional memory devices cannot achieve a multidirection access, in other words, a high dimension access, because, for example, in a two dimension logical bit map space, a plurality of bit data in a X direction can be read by one access, but a plurality of accesses for reading a plurality of bit data in a Y direction is required.
An applicant of the present application has already devised a semiconductor memory device having a chip which includes a multidirection data selection means, by which a multidirection data read and/or write at a high speed is enabled, and having a simple circuit construction by which a low power consumption and a high integration are obtained (US-088,334). However, in this semiconductor memory device, the addressing of data to a memory cell array through the multidirection data selection means depends upon a direction of a data access thereto and is very complex, and thus, the user must cope with a complex addressing process. Also, the circuit construction therefor is usually complex. Further, the selection speed is often lowered.